The present invention relates to a system for testing the state of a clock recovered regenerated on the basis of a digital data input from the outside.
In digital communication, in order to reduce the number of signals to be transmitted, sometimes, only information data is transmitted from the sender to the receiver. In such a case, the receiver executes a clock recovery processing in which a clock is regenerating on the basis of the received information data. Thus, there is a need of making a test by the LSI at the receiving side so as to check whether the clock recovery operation has been normally carried out.
The following is a description on a clock recovery circuit and its operation, and a conventional testing system for testing the clock recovery circuit. For convenience of explanation, is it assumed here that the input data is a 1-bit data having 125 Mbps, and a frequency of a clock source is 25 MHz.
FIG. 1 is a block diagram showing a construction of a conventional clock recovery circuit. This clock recovery circuit 1 includes a 5-muliply circuit 11, a phase control circuit 12, a phase error detector circuit 13, an integration circuit 14 and a sampling circuit 15. The 5-muliply circuit 11 5-multiplies (i.e. increases the signal to a value which is five times more than its original value) a 25 MHz clock supplied from a clock source (not shown) so as to generate a 125 MHz clock. This 5-multiply circuit may be a PLL circuit. The phase error detector circuit 13 detects a time lag between a falling edge of the 125 MHz clock generated by the 5-multiply circuit 11 and a change point of a 125 Mbps input data. The integration circuit 14 integrates a time lag detected by the phase error detector circuit 13.
The phase control circuit 12 controls the phase of the 125 MHz clock generated by the 5-multiply circuit 11 on the basis of the integration by the integrating circuit 14 so that the falling edge of the 125 MHz clock and the change point of a 125 Mbps input data coincide with each other. The sampling circuit 15 samples the input data at a falling edge of the 125 MHz clock phase-controlled by the phase control circuit 12. A recovered clock is obtained by 5-multiplying a 25 MHz clock, and by synchronizing it with a 125 MBPS input data. A recovered data is obtained by sampling the 125 Mbps input data on the basis of the recovered clock thus obtained.
FIG. 2 is a timing chart showing operation timing of the clock recovery circuit shown in FIG. 1. As shown in FIG. 2, the phase of the recovered clock advances with respect to the input data D11 and D12. In order to overcome this problem, the phase of the recovered clock is controlled so as to be delayed. Moreover, the phase of the recovered clock is delayed with respect to the input data D13 and D14. In order to overcome this problem, the phase of the recovered clock is controlled so as to be advanced.
The phase of the recovered clock is controlled so as to be delayed with respect to the input data D15. The legends D21, D22, D23, D24 and D25 denote a recovered data corresponding to respective input data D11, D12, D13, D14 and D15.
As a method of testing a clock recovery operation of an LSI used in a receiving side device, there is an asynchronous test of building up a test environment close to an actual operating environment, and carrying out a test. Moreover, as another testing method, there is a synchronous test of synchronizing a clock recovery operation, and carrying out a test on an LSI tester using a test pattern.
FIG. 3 is a block diagram showing a construction of a conventional asynchronous testing system. This asynchronous testing system comprises a data source 21, a data supply device 22, a 25 MHz clock source 23, a comparator device 24 and a frequency measuring device 25. A clock recovery circuit 1 shown in this figure is the test object. The clock recovery circuit 1 is a circuit having a construction shown in FIG. 1.
The data source 21 has an input data that is to be input into the clock recovery circuit 1. The data supply device 22 supplies the input data of the data source 21 at a 125 Mbps, or in a state that a frequency deviation and jitter are added to the clock recovery circuit 1. The 25 MHz clock source 23 supplies a 25 MHz clock to the clock recovery circuit 1. The comparator device 24 makes a comparison between a recovered data output from the clock recovery circuit 1 and the input data of the data source 21.
The frequency measuring device 25 measures a frequency of a recovered clock outputted from the clock recovery circuit 1. When the comparison of the recovered data and the input data shows that the two match with each other further, when the measured frequency of the recovered clock coincides with the frequency of the input data, then it is decided that the clock recovery circuit 1 is working normal.
Next, an explanation will be given about the synchronous test. In the synchronous test, a 125 Mbps clock is supplied directly to the clock recovery circuit which is a test object, at a test pattern. Moreover, a 125 Mbps input data is supplied directly to the clock recovery circuit at a test pattern. Then, a confirmation is made whether or not a recovered data outputted from the clock recovery circuit coincides with a test pattern of the input data inputted to the clock recovery circuit. If the recovered data and the test pattern coincide with each other, a decision is made that the clock recovery circuit 1 is working normal.
There is a drawback in the aforesaid conventional asynchronous test that a storage device for storing the input data, a comparator device and the like are required. Accordingly, the structure of the testing system complicated. Moreover, in order to measure a frequency of recovered clock, a number of pulses in a predetermined time must be measured. For this reason, there is a problem that a testing time becomes long.
On the other hand, in the aforesaid synchronous test, an LSI tester operable at frequency as high as a 125 MHz is required. However, a high speed LSI tester having an operating frequency of 100 MHz or more is very expensive. For this reason, in general, there is a problem that it is difficult to use many high speed LSI testers, and a testing cost becomes high.
It is an object of the present invention to provide a recovered clock testing system which can test a high frequency clock recovery operation using a cheap low speed LSI tester with respect to an LSI used in a receiving side of digital communication.
The testing system according to the present invention comprises a delay circuit which holds a 10-bit data of a 125 Mbps recovered data outputted from a clock recovery unit, an adder circuit which operates the total sum of 10 data held in the delay circuit, a edge detection circuit which detects a change of the recovered data, and a 4-bit flip-flop circuit which samples the operation result of the adder circuit when the recovered data changes, and outputs it as a test result.
Further, the present invention provides a testing system including a pseudo random number generating circuit which generates a pseudo random number on the basis of a 125 MHz clock outputted from a clock multiply circuit included in a clock recovery circuit, and an expected value generating/comparator circuit which collates a 125 Mbps recovered data outputted from the clock recovery circuit 1 with an expected value data each 5 bits or 15 bits, and then, outputs the collation result as a 1-bit test output
According to the invention, the clock recovery circuit and the testing system included in the LSI are operated by a 125 MHz high frequency clock, however, a test output is a 25 MHz low speed data in the light of the outside of LSI. All recovered data information are reflected in the test output.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.